Hadi Esmaeilzadeh - Department of Electrical and Computer Engineering University of Tehran, Tehran, Iran
Ardavan Pedram - Department of Electrical and Computer Engineering University of Tehran, Tehran, Iran
Armin Alaghi - Department of Electrical and Computer Engineering University of Tehran, Tehran, Iran
Babak Nadjar Araabi - Department of Electrical and Computer Engineering University of Tehran, Tehran, Iran

Exploiting neural networks native parallelism and interconnection locality, dedicated parallel hardware implementation of neural network is essential for effective use of these strong computation facilities in time-critical applications. The architecture proposed in this paper is a parallel stream processor which can be configured as a number of different neural networks. The architecture is an especial collection of configurable data-flow processing elements with a custom FIFO-based cache architecture which is designed to fill the gap between the slowness of the external memory and the processor. Streams of data flow through the parallel processing elements and computations are performed based on the headers of the data streams. Also the header of a stream configures each processing element to perform a desired computation on the up coming data. The data-flow base of the architecture brings up a high degree of flexibility and scalability for the proposed stream processor. The stream processor is synthesized targeting an ASIC standard cell library and also realized on an FPGA. Employed for hand-written digit pattern recognition task, a neural network is mapped on the realized hardware and the implementation and speedup achievements are presented.