A Low-power, Compact, Dynamic D-type Flip-Flop for Implementation of the Digital Delay Line in a D ecision Feedback Equalizer

A low-power, dynamic, negative-edge-triggered D-type flip-flop (D-NETFF) intended for the digital delay line in a decision feedback equalizer is proposed. The performance of the D-NETFF has been compared with that of a standard, static D-type flip-flop topology employing master-slave latches in a90nm CMOS technology based on HSPICE simulations. The positive-edge-triggered equivalent of the proposed D-type flip-flop (D-PETFF) as well as the standard static flip-flop have been designed and implemented in a 2μm CMOS technology and their performance has been characterized. Comparedwith the static flip-flop, the dynamic flip flop consumes less power, operates at higher speeds, and employs a smaller number of transistors

Keywords:

Decision feedback equalizer , dynamic D Flip-flop , high-speed , low-power