A Low-Power 10-bit 100-MS/s Pipelined ADC in 90-nmCMOS Technology

This paper presents a low power CMOS pipelinedanalog-to-digital converter (ADC) operating in a 1.5-Vsupply voltage. This low power ADC utilizes the foldedcascade Opamp and the comparators are based on dynamiclatches with positive feedback to further save the power. Thewhole structure of the ADC is based on fully circuits toenhance the linearity. Furthermore, the bootstrappedswitches are used in the input side of the ADC, to overcomethe nonlinearity problems of the simple MOS switches. TheADC was designed to operate at 100 MS/s in a 90nm CMOSprocess, where simulated results using ADS2009, show thepeak SNDR and SFDR of the ADC to be 58 dB (9.38 ENOB),and 61 dB respectively. The ADC consumes less than 17 mWwith 100 MHz sampling frequency