Akram Reza - Sama technical and vocational training college Islamic Azad University Karaj Branch Karaj Iran
Midia Reshadi - Department of Computer Engineering Islamic Azad University Science and Research Branch Tehran Iran

Disproportion between gate and wire delays on chip is aggravated by technology shrinking in the deep submicron (DSM) domain. Thus, Network on Chip is proposed to address DSM problem. In this paper we propose a low latency NoC switch based on Deterministic Finite State Machine and port locking mechanism which is implemented by multiplexer. Routing and arbitration operations are done in only one clock. In addition, switch area is reduced significantly in comparison to conventional NoC switches. Proposed Switch is described in VHDL; validation and simulation are performed by ModelSim. Synthesis is executed by Leonardo Spectrum- 98 tool in ASIC and FPGA designs.

network on chip,switch ,finite state machine ,buffering strategy