Development of a Co-Simulation Environment in a System Level Design Methodology

In this paper, we present a cycle-accurate co-simulation environment developed for verification and performance evaluation of OO-ASIP in our ODYSSEY design methodology. This environment is composed of a processor Instruction Set Simulator (ISS) integrated with a hardware simulator and communicate with it through socket connections. We demonstrate the effect of our co-simulation method in increasing speed of simulation without missing cycle accuracy of results by means of two case studies.

Keywords:

ASIP , ODYSSEY , Co-simulation