A Uniform BIST Strategy for CPU Data Path in RT Level of Abstraction

The flexible DFT strategy helps designers control the eventual cost of test during the chip design phase. To reach a uniform test strategy for CPU data path, we use S-graph information. But register files and inter nal memory structures cannot be easily represented by S-graphs. In most processors investigated, one can find some sort of internal memory like general-purpose registers, stacks or queues. The control hardware and addressing schemes of such structures make it difficult to test them. We design a wrapper around these structures to isolate them from data path and incorporate them to S-graphs applications. These compatible S-graphs provide a uniform BIST strategy for the whole data path. The wrapper design can test itself concurrently with other modules so it can reduce the test application time. We apply our method on SAYEH CPU as a vehicle.

Keywords:

Compatible S-graph , general-purpose registers , BIST