A Transistor-Level Placement Tool for Asynchronous Circuits

Although asynchronous circuits are accepted as low-power, low-EMI and high-performance circuits, the roadblock to wide acceptance of asynchronous design methodology is poor CAD support, especially physical design tool. There are few academic design tools for asynchronous circuit design and synthesis, but there is neither a published tool nor a published document on physical design of these circuits. Since there are noncomplementary CMOS circuits in the netlist synthesized using Caltech synthesis method, the commercial cell-based placement tools can’t be used. In this paper we have presented a design flow for placement of asynchronous circuits at transistor-level considering their timing constraints.

Keywords:

Asynchronous Circuit , Physical Design , Placement and Isochronic Fork