Evaluation of a Dependable Architecture

Functionality of Master/Checker (M/C) mode is based on the redundancy of the processors supported by most modern processors. This paper presents an experimental evaluation of the M/C mode in a 32-bit Pentium  processor system using power-supply disturbance (PSD). The results of PSD show that the M/C mode has only 67.13% error detection coverage. The low coverage is caused by the crashes in the Master processor as the result of voltage fluctuations. Use of a watchdog timer may raise the coverage up to 99.73%. Moreover, the correctness of the results produced by the Master processor has been checked. In many cases, the results were correct while the Checker processor announces an error.

Keywords:

Master/Checker Mode , Fault Injection , Experimental Evaluation , Watchdog Processor