A 2.7 to 10.6 GHz High-Flat-Gain CMOS Low-Noise Amplifier for UWB Applications

In this paper, a low-power ultra wideband (UWB) low-noise amplifier (LNA) with high and flat gain is proposed. By using an input common-gate stage, an input matching from 3.1 to 10.6 GHz is achieved. The output matching is obtained by using the output matching network including output buffer, capacitor and inductor. In proposed LNA, current-reused technique is adopted in order to reduce the power dissipation. The proposed LNA provides high gain with excellent flatness and low noise figure over broadband while it has very good stability too. The LNA was simulated with a TSMC 0.18-μm CMOS technology. The input and output reflection coefficients are less than -11 dB from 3 to 11GHz and -10 from 2.3 to 12 GHz, respectively. The noise figure of the proposed LNA remained under 4.3 dB from 2.2 to 10.7 GHz with minimum value of 3.12 dB. Additionally, high and flat gain of 13±1.8 dB is achieved for whole the ultra band. The linearity of input third-order intercept point is -7.76 dBm and P-1dB compression is -17 dBm. The power consumption at 1.5-V supply voltage without an output buffer is only 11 mW.

Keywords:

CMOS , low-noise amplifier (LNA) , ultra-wideband (UWB) , common-gate , noise figure (NF)