A Novel Low Phase Noise Low Power Digitally- Controlled-Oscillator in 90nm CMOS Technology for ADPLL Application

A novel structure with low phase noise and low power dissipation CMOS Digitally-Controlled-Oscillator (DCO) is presented. Two effective techniques including adding start-up circuit and utilizing top current source, are used in order to optimize the phase noise and decrease the power consumption, simultaneously. The performance of the proposed DCO well meets all the requirements for All-Digital Phase Locked-Loop (ADPLL). Simulation results are obtained by the Cadence IC Design in TSMC 90nm CMOS technology with Spectre simulator. The measured phase noise at 500 KHz and 1 MHz offset from the 2.440 GHz carrier is around -113.2 dBc/Hz and - 120 dBc/Hz, respectively, while the DCO consumes 3 mw at the 1.2 volt supply voltage and finally, FOM is -182 dBc/Hz.

Keywords:

component , Start-up , Digitally-Controlled- Oscillator , Carrier , All-Digital Phase-Locked Loop , Phase Noise , Power dissipation