On a Low-Power High-Speed MAP Turbo Decoder Design
Publish place: 8th Annual Conference of Computer Society of Iran
Publish Year: 1381
Type: Conference paper
Language: English
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Document National Code:
ACCSI08_016
Index date: 7 February 2008
On a Low-Power High-Speed MAP Turbo Decoder Design abstract
Turbo codes have become part of the third generation W-CDMA systems because of their extraordinary coding performance. However, decoder implementation in commercial systems suffers from power, latency and complexity limitations. Here, we address new optimization techniques to overcome these problems. This paper makes two contributions. First, SISO block is designed in a pipeline approach which increases the speed about two times. Second, it is shown that using a circuit block instead of memory for generating the interleaved addresses, reduces the power and area exponentially as the interleaver length increases.
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On a Low-Power High-Speed MAP Turbo Decoder Design authors
Maryam Mizani
Department of Electrical & Computer Engineering Tarbiat Modares University Tehran, Iran
Abdolreza Nabavi
Department of Electrical & Computer Engineering Tarbiat Modares University Tehran, Iran
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