Improved Buffer Insertion for Simultaneous Crosstalk-Delay Optimization

As integrated circuits (ICs) are scaled into nanometre dimensions and operate in gigahertz frequencies, interconnects have become critical in determining system performance and reliability. In this paper we propose a new approach to investigate Buffer insertion with wire sizing and spacing which helps to have simultaneous optimization of interconnect delay and crosstalk noise in deep submicron VLSI circuits. The optimization problem is modelled by solving a new cost function to find a minimum cost for both crosstalk noise and delay which are conflicting in nature. Through MATLAB software, a system of three coupled wires is modelled as a RC distributed network. The results indicate the number of optimum available solutions including wire sizing, wire spacing and buffer insertion in which crosstalk reduction techniques can be useful for both crosstalk noise and delay.

Keywords:

Nano scale , Interconnect optimization , wire sizing , wire spacing , buffer insertion , optimization algorithm , delay , crosstalk