A Mokarram - Microelectronics Research Laboratory Urmia University Urmia, Iran
A Khoei - Microelectronics Research Laboratory Urmia University Urmia, Iran
Kh Hadidi - Microelectronics Research Laboratory Urmia University Urmia, Iran

In this paper, a CMOS four quadrant multiplier based on flipped voltage follower and differential squaring circuit is presented. The proposed circuit has a compact architecture operating at higher speed and higher input voltage range compared to previously presented structures. The transistors operate in the both saturation and ohmic regions. The circuit operates with a single supply voltage of 3.3V in a 0.35 $m CMOS technology the total harmonic distortion (THD) is less than 1.1%, the linearity error is also less than 3%, -3db frequency is more than 180 MHz and the voltage input range is 3 p p V . Simulation results are given to verify the functionality of the proposed multiplier.

analog multiplier; four quadrant multiplier; defuzzification; CMOS;