Concurrent Error Detection in Residue Circuits By Using Time Redundancy
Publish place: 16th Iranian Conference on Electric Engineering
Publish Year: 1387
نوع سند: مقاله کنفرانسی
زبان: English
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شناسه ملی سند علمی:
ICEE16_350
تاریخ نمایه سازی: 6 اسفند 1386
Abstract:
Concurrent error detection (CED) techniques are widely used to enhance system dependability. All CED techniques introduce some form of redundancy. CED schemes could often correct some errors, creating a fault tolerant system. In this paper a novel fault tolerant method is proposed through combining information and time redundancy. This method can be used in various types of arithmetic circuits. As a proof of concept we applied time redundancy to a residue adder. In comparison with nonredundant residue adder and other fault toleranc schemes such as Re-computation with Duplication with Comparison (REDWC), our method - Quadruple Cycle Residue Redundancy (QCRR) adder- results in 22~50% reduction in hardware complexity. This approach introduces large savings on the ALU as a whole and only causes a reasonable increase in delay.
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Authors
Rana Forsati
Computer Engineering Dep. Azad University of Qazvin, Qazvin, Iran
Karim faez
Electrical Engineering Dep. AmirKabir University of Technology,Tehran, Iran
Farnaz Moradi
Computer Engineering Dep. Azad University of Qazvin, Qazvin, Iran
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