A very low-power 8 GHz frequency divider in 180nm CMOS technology

A very low-consumption 8 GHz frequency divider in 180nm CMOS technology is presented. The MOS switching loss and transistor sizing optimization techniques were implemented to reduce power consumption and increase the speed of the proposed circuit, leading to an increase in the overall performance of the system. In addition used several trade-off between supply voltage, gain, voltage swings, bandwidth, distortion, input offset, linearity and power consumption parameters lead to a multi-dimensional optimization problems. Such trade-off throughout the design process requires intuition and experience to reach an acceptable compromise. The frequency divider speed is about 8 GHz. A clock input voltage was applied at a similar speed for simulation purposes. Power consumption of the circuit was obtained as less than 114 mW (supply voltage: 1.8V).The H-SPICE software was used for simulation and further analysis of the results.

Keywords:

Frequency divider , Clock input voltage , TSPC و E-TSPC , CMOS technology