A New Approach to Evaluation of Fault Tolerant Cascading TMR Systems Suitable for FPGA Based Application

Triple Module redundancy (TMR) is a commonly used approach to increase reliability in space applications. Applying this method, triple modules and voting circuits are implementable in a Field Programmable Gate Array (FPGA). In TMR systems when a single event upset (SEU) occurs, the voting circuit overrides the output of the module receiving the SEU and takes the majority rule from the other two modules. The proposed fault tolerant TMR based circuit utilized for the combinational and sequential logic at gate level was evaluated using a VHSIC (Very High Speed Integrated Circuit) Hardware Description Language (VHDL) code in a structured yet high level coding style to obtain the required redundancy. This method is a pattern based approach that has the ability to adjust to any desired function with any level of redundancy. Results show that the proposed TMR system is capable of withstanding SEU type faults in an efficient voting scheme.

Keywords:

Fault tolerance , single event upsets (SEUs) , triple modular redundancy (TMR , , VHSIC( Very High Speed Integrated Circuit Hardware Description Language (VHDL)