A Technique For Testing Network Connections In Parallel With Mesh Topology

Publish Year: 1394
نوع سند: مقاله کنفرانسی
زبان: English
View: 601

This Paper With 15 Page And PDF and WORD Format Ready To Download

  • Certificate
  • من نویسنده این مقاله هستم

استخراج به نرم افزارهای پژوهشی:

لینک ثابت به این Paper:

شناسه ملی سند علمی:

NSOECE04_081

تاریخ نمایه سازی: 9 مرداد 1395

Abstract:

In this paper, we connections between switches in the mesh network topology in a parallel way we've tested. The method is based on a built-in self-test, the use of buffers FIFO Each of the switches, test all connections between switches is done in parallel, not only test application time, but the area overhead of the network is reduced. The demands of future computing and high-density integrated circuit design challenges for nanometer technology requires new methods and styles in the design, which is certainly the method of high performance and low power consumption as well as high resistance to noise and changes The process will have. One of the main problems, mechanism of communication that must increase the number of blocks or cells that can be embedded in a chip, is established. The bus-based systems and point-to-point communication strategy can not easily embedded cores inside a single chip together a large number of systems-on-chip designers, and so great is faced with many restrictions. Network-on-chip communication infrastructure, one of the key technologies that many design constraints-on-chip systems for large multi-core processors to eliminate the source of the emergence of system-on-chip with high computing power low power consumption. This treatise on network-on-chip testing of the communication infrastructure is concentrated. Motivation to do it is with the continuing miniaturization of circuits in nanometer technology, flaws and bugs a serious challenge for manufacturing integrated circuits with millions of transistors will be. So solutions need to be network-on-chip communication infrastructure bug detector is developed. In this study, a built-in self-test procedure to test the link between high-performance switches have been suggested to play a role in significantly reducing application time-tested play. In this way, using the built-in self-test, simultaneous testing of all network-on-chip communication infrastructure links in a testing session provides a fully parallel so that all communication links are tested when user testing can be minimized

Keywords:

Built-In Self-Test , Hearing , Connections , Network With Mesh Topology

Authors

javad mohajerani

Department of computer engineering, Baft branch, Islamic azad university, Baft, Iran

farokh kourpoi

Department of computer engineering, Baft branch, Islamic azad university, Baft Iran

مراجع و منابع این Paper:

لیست زیر مراجع و منابع استفاده شده در این Paper را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود Paper لینک شده اند :
  • P. Magarshak, PG Paulin, _ System- on-Chip Nanometer beyond the ...
  • Z. Chen, I. Koren, "Crosstalk minimization in Three-layer Hvh Channel ...
  • AB Kahng, S. Muddu, E. Sarto, R. Sharma, "Strategies for ...
  • H. Zhou, DF Wang, "Global Routing with Crosstalk Constraints , ...
  • W. Chen, SK Gupta, MA Breuer, "Test Generation for Crosstalk ...
  • Itazaki N., Y. Matsumoto, K. Kinoshita, "An Algorithmic Test Generation ...
  • Ktlee, C. Nordquist, J. Abraham, " Automatic Test Pattern Generation ...
  • A. Sinha, Skgupta, MA Breuer, "Validation and Test Generation for ...
  • C.crecu, A.ivanov, R.saleh, Pppande, "Testing Network on Chip C ommunication ...
  • Mhtehranip our, N.ahmed, M.nourani, "Testing SoC Interconnects for Signal Integrity ...
  • C.crecu, , Pppande, A.ivanov, R.saleh, _ Network- on-Chip interconnect Bist ...
  • M. Guviello, S. Dey, X. Bai, Y. Zhao, "Fault Modeling ...
  • PP Pande, C. Grecu, M. Jones, A. Ivanov, and R. ...
  • J. Duato, S. Yalamanchili, and L. Ni, Interc onnection Networks-An ...
  • I. Saastamoinen, M. Alho, and J. Nurmi, _ _ Network- ...
  • H. Wang, L.-S. Peh, and S. Malik, "On-chip Power-driven Design ...
  • M icro architecture S in Networks, " in Proc. 36th ...
  • J. Oberg, "clocking strategies for network on chip", Network on ...
  • C. Grecu, P. Pande, A. Ivanov, and R. Saleh, "Timing ...
  • FG Moraes, N. Calazans, A. Mello, L. Moller, and L. ...
  • infrastructure for low area overhead packet- switching networks on chip, ...
  • J. Hu and R. Marculescu, "routing for networks- on-chip Dyad-Smart, ...
  • نمایش کامل مراجع