The Reduction of Thermal Energy on the 3-Dimensional NOC byProviding an Efficient Mapping Based on Beehive Structure

The concept of ‘Network on Chip’ includes processing elements each of which is placed together with a specific functionality in a substructure communication based on their applications. In the world of the systems on the chips, the main goal of the network on chip isto present a solution for simultaneous access to the performance, development and flexibility. Topology, mapping, routing algorithms, power, throughput, latency and performance overhead area and the complexity of connections are among the things that are taken intoconsideration while designing systems on chips. In order to optimize power consumption and delay, the researchers tried to change each of the properties of the network on chip. Although different and optimal mapping methods have been proposed so far and achieved good results in reducing latency and power consumption, but substructures we face the problems of power and temperature control in designing the three-dimensional. In this study, a communicational substructure based on three-dimensional structure of the regular six-sided architecture similar to a beehive is presented, which is improved with an efficient mapping based on spiralmapping. This presentation has been able to optimize the features of a network on chip and has managed a solution to reduce communication cost and power consumption and as a resultdiminishes the average energy consumption across the network.

Keywords:

network on chip , mapping , graphic tasks , consumption power , topology , energy