Design of a VLSI Hamming Neural Network For arrhythmia classification

The implantable cardioverter defibrillators (ICDs) detect and treat dangerous cardiac arrhythmia. This paper describes a VLSI neural network chip to be implemented using 0.35μ CMOS technology which acts as an intercardia tachycardia classification system. The Hamming net used to classify non binary input pattern and also reduce impact of noise, drift and offset inherent in analog application.

Keywords:

Implantable tachycardia arrhythmia classifier , Neural Network , Hamming Net