Power and Speed Analysis of CMOS-based Multipliers using VEDIC techniques

Multipliers are one of the most important components in design of both digital and analog circuits. The design and structure of multipliers play a significant role to determine speed and power consumption of processing units as the core component of electronic devices. In this paper, we design ۴×۴ and ۸×۸ multipliers in layout level to extract important design parameters. VEDIC mathematic techniques and CMOS logic are used to obtain a tradeoff between speed and power efficiency. Our results show that voltage range between ۱.۵v and ۲.۵v is the efficient range to perform high speed and low power multiplication.

Keywords:

Multiplier , VEDIC , L-edit , CMOS , Low power