Low Power and High Performance Clock Delayed Domino Logic using Saturated Keeper in sub 100nm Technologies
عنوان مقاله: Low Power and High Performance Clock Delayed Domino Logic using Saturated Keeper in sub 100nm Technologies
شناسه ملی مقاله: ICEE14_285
منتشر شده در چهاردهمین کنفرانس مهندسی برق ایران در سال 1385
شناسه ملی مقاله: ICEE14_285
منتشر شده در چهاردهمین کنفرانس مهندسی برق ایران در سال 1385
مشخصات نویسندگان مقاله:
A. Amirabadi - Nanoelectronics center of excellence University of Tehran
A. Chehelcheraghi - Department of Electrical and Computer Engineering, University of Shahid Beheshti, Tehran, Iran
S. H. Rasouli - Nanoelectronics center of excellence University of Tehran
A. Seyedi - Nanoelectronics center of excellence University of Tehran
خلاصه مقاله:
A. Amirabadi - Nanoelectronics center of excellence University of Tehran
A. Chehelcheraghi - Department of Electrical and Computer Engineering, University of Shahid Beheshti, Tehran, Iran
S. H. Rasouli - Nanoelectronics center of excellence University of Tehran
A. Seyedi - Nanoelectronics center of excellence University of Tehran
In this work, domino logic with a saturated keeper technique is proposed. The circuit, which is used to implement the technique, is as simple as the utilized NOT gate in standard domino. By using the simple structure, we can obtain better performance, noise immunity, and lower power consumption. The simulation results for a 70 nm CMOS technology show an improvement between 7% and 62.5% in delay and 9% and 14% in power consumption, over its previous suggestions.
صفحه اختصاصی مقاله و دریافت فایل کامل: https://civilica.com/doc/54956/