Hassan Abdollahi - Islamic Azad University, south Tehran Branch and Shahid Sattari Air University,
Abdolreza Nabavi - Tarbiat Modarres University.
Satar Mirzakuchaki - Iran University of Science and Technology
Afsaneh Haghnegahdar - Iran University of Science and Technology

In this paper, we introduce a new low-power SRAM cell with seven transistors. The design is based on energy recovery and driving source line cell that reduces the power dissipation associated with write operations. The new memory is designed using 0.6μm CMOS technology and operates in voltage mode with 5 Volts power supply. Simulation results indicate that the energy saving is improved about 20% in read cycle and 40% in write cycle at 166MHz, compared to conventional design. The layout penalty of seven-transistor cell is negligible compared to 6-transistor SRAM.

Memory, Low power, High speed and SRAM