A new Implementation of DA-based IIR Filters on FPGA
Publish place: 12th Iranian Conference on Electric Engineering
Publish Year: 1383
نوع سند: مقاله کنفرانسی
زبان: English
View: 1,983
This Paper With 5 Page And PDF Format Ready To Download
- Certificate
- من نویسنده این مقاله هستم
استخراج به نرم افزارهای پژوهشی:
شناسه ملی سند علمی:
ICEE12_010
تاریخ نمایه سازی: 13 مهر 1387
Abstract:
FPGAs with their flexibility, parallelism,high speed, and fast time-to-market are increasingly being utilized in signal processing applications. In this approach, implementation of MAC processors is one of the most challenging design tasks. One of the most suitable methods of MAC implementation on FPGAs is
Distributed Arithmetic. This bit-serial word-parallel method results in very area efficient implementations, reducing the resource utilization up to 80% [1].
Although this method is very efficient in FIR filters, its application in IIR filters is very limited because of the inherent feedback delay in these filters, which both introduces design complexity and speed degradation. In this article, a new design of DA-based IIR filters, based on a new accumulator design, is xplained, which solves the limiting problems, and achieves good area and speed performance. Results for an exemplary implementation are presented.
Keywords:
Authors
H Khoshbin Ghomash
Ferdowsi University of Mashhad
A Joulaian
Ferdowsi University of Mashhad
S. M. Sajjadi
Ferdowsi University of Mashhad-Khorasan Basij Electronics
مراجع و منابع این Paper:
لیست زیر مراجع و منابع استفاده شده در این Paper را نمایش می دهد. این مراجع به صورت کاملا ماشینی و بر اساس هوش مصنوعی استخراج شده اند و لذا ممکن است دارای اشکالاتی باشند که به مرور زمان دقت استخراج این محتوا افزایش می یابد. مراجعی که مقالات مربوط به آنها در سیویلیکا نمایه شده و پیدا شده اند، به خود Paper لینک شده اند :