A 10-MHz Low-Distortion Low Power CMOS Line Driver Suitable for High Speed Data Transmission Applications

This article describes a large bandwidth and low distortion line driver in a .35μ m CMOS process. The line driver drives a 75 Ω resistance load. Its power consumption is 140 mW from 3.3 Volts supply. It has relatively high –3dB bandwidth (260 MHz) with good phase margin of about 70 degrees. It shows very low THD (-74.5 dB) when drives the load with a 3.3 V peak to peak sine wave at 10 MHz frequency. This architecture reduces the distortion by locating the input differential pair in the feedback loop and eliminating the distortion of the feedback transistors, specially at high frequencies. Thus, it improves the linearity of the output voltage in comparison with previous designs.

Keywords:

line driver , linearity , THD , folded cascode , class A/B , distortion