Ladan alaee - Department of computer,Science and Research branch,Islamic Azad university, Tehran,Iran,
samira saeidi - Department of computer,Islamic Azad university,Tehran,Iran

In the last two decades, the network on chip as a way to reach a large number of processors on the chip is taken into account. The use of integrated circuits, the occurrence of challenges, including hardware complexity, power consumption and high reliability has led issue that these challenges must be addressed by chip designers.mesh topology is favored by regularity and layout efficiency and diversity in size and shape of modules used in practical NOCs has resulted in use of irregular meshes. However, regular mesh routing algorithms not usable for irregular mesh and modified routing algorithms are needed. In this, we propose a fault tolerance and deadlock free routing algorithm for irregular 2-dimentional mesh NOCs. This algorithm eliminate the constraint of OAPR algorithm to aligne all OIPs on the east edge in OIPs vertically overlapped. therefore, it increase OIPs placement flexibility.in this algorithm virtual channel is not used. The implementation is conducted using the Xmulator simulator. Experimental result show that the proposed algorithm has dead lock free, fault tolerance and higher performance in term of average message latency and power consumption compared to OAPR algorithm from 5 percent to 50 percent, for irregular mesh NOC.

Network-on-chip, Deadlock, fault tolerance,Power consumption, latency, routing algorithm