Mahmoud Zangeneh - The authors are with the Advanced VLSI Lab., School of Electrical and Computer Engineering, College of Engineering,University of Tehran, Tehran, Iran.
Nasser Masoumi - The authors are with the Advanced VLSI Lab., School of Electrical and Computer Engineering, College of Engineering,University of Tehran, Tehran, Iran.

This paper presents an accurate methodology for the optimum interleaved-repeater positioning in global interconnects. We have compared the analytical delay uncertainty of available repeater insertion techniques and derived analytical expressions for extracting a new optimum value for the relative position ratio of the interleaved interconnects. We have used the simple yet-realistic α-power law for MOS devices in the proposed model in order to increase the accuracy of the methodology. The new positioning method has been proven to minimize the delay uncertainty caused by the coupling capacitance of the switching adjacent lines. The measured uncertainty of the proposed methodology was less than 10% for all beyond 100-nm scaled technology nodes. It is also shown that the proposed strategy offers lower propagation delay sensitivity to variations of a segment length in comparison with commonly used repeater insertion techniques. Accordingly, using the proposed methodology, we achieve a maximum sensitivity reduction of 33% for 65-nm technology, 51% for 45-nm technology and 34% for 32-nm technology node.

Repeater insertion, interconnect, delay uncertainty, coupling capacitance, switching pattern, crosstalk, VDSM