E. Rahiminejad - the Integrated Systems Lab., EE Dept., Ferdowsi University of Mashhad, Iran.
R. Lotfi - the Integrated Systems Lab., EE Dept., Ferdowsi University of Mashhad, Iran.

This work describes a modified architecture for integrating analog-to-digital converters (ADC) for use inbiomedical or any other applications where the input signal has small and slow variations. In this architecture, insteadof digitizing every new analog sample independently, the difference of the new sample with the previous sample isconverted to digital. With this idea, the power consumption of the integrating ADC can be considerably reduced. In this paper, design considerations and simulation results of an 8- bit, 4 kS/s ADC in a 0.18μm CMOS technology areaddressed to show the effectiveness of the idea. The proposed ADC is more power efficient when used for input signals that are very slow and have small variations in voltage amplitude. Simulations confirm that the proposedADC architecture shows more than 80% power saving compared to conventional architectures for an input signalamplitude of 0.2 VFS.

Low-power, integrating ADC, biomedical applications, signal-specific