A 5.3-9.3 fJ/Conversion-Step 4-32 MS/s 10 bit Asynchronous SAR ADC with Optimized DAC Timing Strategy in 0.13 μm CMOS
Publish place: Journal of Electrical Systems and Signals، Vol: 2، Issue: 2
Publish Year: 1393
نوع سند: مقاله ژورنالی
زبان: English
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شناسه ملی سند علمی:
JR_JESS-2-2_001
تاریخ نمایه سازی: 19 شهریور 1396
Abstract:
In this paper, a low power SAR Analog to Digital Converter (ADC) with a resolution of 10 bits and a sampling rate of 4 to 32 MS/s is proposed. It utilizes an asynchronous process with an optimized D/A timing strategy to increase its sampling frequency. This ADC is simulated in a 130-nm CMOS technology with two power supplies of 0.6 V and 1.2 V. It achieves an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM = 5.3 to 9.3 fJ/conv.-step.
Keywords:
Analog to digital converter , asynchronous process , power efficiency , asynchronous clock generator circuit , low power designs
Authors
Mohsen Dashtbayazi
Department of Electrical Engineering, Ferdowsi University of Mashhad, Iran
Mohammad Taherzadeh-Sani
Department of Electrical Engineering, Ferdowsi University of Mashhad, Iran
Samaneh Babayan Mashhadi
Imam Reza International University
Ehsan Rahiminejad
Department of Electrical Engineering, Ferdowsi University of Mashhad, Iran