Mohsen Dashtbayazi - Department of Electrical Engineering, Ferdowsi University of Mashhad, Iran
Mohammad Taherzadeh-Sani - Department of Electrical Engineering, Ferdowsi University of Mashhad, Iran
Samaneh Babayan Mashhadi - Imam Reza International University
Ehsan Rahiminejad - Department of Electrical Engineering, Ferdowsi University of Mashhad, Iran

In this paper, a low power SAR Analog to Digital Converter (ADC) with a resolution of 10 bits and a sampling rate of 4 to 32 MS/s is proposed. It utilizes an asynchronous process with an optimized D/A timing strategy to increase its sampling frequency. This ADC is simulated in a 130-nm CMOS technology with two power supplies of 0.6 V and 1.2 V. It achieves an ENOB greater than 9.3 bits for its full sampling-rate range (4 to 32 MS/s) with an FOM = 5.3 to 9.3 fJ/conv.-step.

Analog to digital converter; asynchronous process; power efficiency; asynchronous clock generator circuit; low power designs