Morteza Shahedifar - Electrical and Computer Engineering faculty, University of Tabriz, Tabriz, Iran
Mina Zolfy - Electrical and Computer Engineering faculty, University of Tabriz, Tabriz, Iran
Masoom Nazari - Electrical and Computer Engineering faculty, University of Tabriz, Tabriz, Iran
Pejman Gasemi - Electrical and Computer Engineering faculty, University of Tabriz, Tabriz, Iran

In applications such as distant discovery operation, using SRAM based FPGAs has great consideration because of its ability to reconfiguration. Results of tests on SRAM based FPGAs show that these segments are very sensitive to space radiations and their SEU rate is very high. Hamming code is used in contrast to SEU in SRAM based FPGAs configuration bits. This code is able to correct single bit errors, but with advances in semi conductive technology and increase in memory density, a full energy space particle can converse several adjacent memory bits simultaneously. In this paper, a method was proposed based on genetic algorithm which aims to find a balanced improved matrix for error correction codes used in switch module and LUTs. After applying the proposed method, almost all adjacent 2 or 3 bit errors in corresponding codes (efficiency is about 95% only in 16 bit codes) is recognizable which shows many improvement over bit positioning. However, this method is concomitant with redundancy in needed gates for decoding. Therefore, preliminary model was improved and the ability to compromise between hardware content and efficiency was added to the model. Thus, this method can be used in two ways: 1- for reduction in hardware content, 2- for efficiency improvement. After applying the improved model in desired codes, till the extreme time that hardware redundancy is allowed, the efficiency for all codes will be 100% and where the redundancy is prohibited.

FPGA, SEU, Genetic Algorithm, SRAM