Marzieh Lenjani - Multimedia Processing Laboratory, School of Electrical and Computer Engineering, University of Tehran
Mahmoud Reza Hashemi - Multimedia Processing Laboratory, School of Electrical and Computer Engineering, University of Tehran

On-chip network interconnections or Network-on- Chip (NOC) is viewed as a possible solution to global wiring issues in highly integrated complex systems. In current NoCs and in order to promote system level integrity, there is a growing need to provide different traffic classes, each with a different Quality-of-Service guarantee. In synchronous NOCs guaranteed service is provided by reserving time slots. Asynchronous NOC implementation, on the other hand, eliminates the need for synchronization when crossing clock domains. In asynchronous NOCs there is no notation of time and arbitration. Any delay in arbitration or refusing requests in arbitration results in the accumulation of data in switch buffers. In this paper a novel arbitration scheme for clockless NOCs has been proposed that is able to service a connection without any halt or jitter in streaming. Consequently, links with a burst traffic pattern and guaranteed bandwidth requirement can be implemented without any large buffers. Simulation results indicate that the proposed method is able to reduce switch buffer size, and hence power consumption in any NoC platform that is providing guaranteed bandwidth requirements in applications with burst data characteristics. For instance, in an MPEG-2 decoder mapped to a 3x2 mesh with 8 guaranteed bandwidth channels in each port, the proposed arbitration scheme is able to reduce the buffer size by 25%. The improvement increases to %47 for a JPEG2000 encoder mapped to a 3x3 mesh.