Logic Gate Implementation Using UTB-SOI Junction-Less Triple Gate MOSFETs With Dual Material Gate

In the present work, a simulation study of Logic Gates is implemented using Ultra-Thin Body Silicon-On-Insulator (UTB-SOI) Junction-Less Triple Gate metal oxide semiconductor field effect transistors(MOSFETs) with Dual Material Gate (JL-TG-DMG) structure. The effect of channel length scaling on thedevice performance in terms of parameters such as threshold voltage, Drain induced barrier lowering (DIBL),and Sub-threshold Swing (SS) is investigated. Plus, the logical Gates such as AND, NAND, and NOT by usingthe proposed structure is simulated. Simulation results show that the proposed UTB-SOI JL-TG-DMG hasexcellent digital performance, and near ideal SS.

Keywords:

Junction-Less FETs , SS , DIBL , Triple-Gate , Dual Material Gate , Logic Gates