A Low-Power, High Bandwidth, 2.5 Gb/S CMOS optical receiver

A low power 2.5Gb/S CMOS optical receiver is presented in this paper. The circuit consists of a transimpedance amplifier (TIA) and 1 stage of limiting amplifier (LA). In this design, a TIA is used for bandwidth extension of the receiver and 1 stage of limiting amplifier with Inductive peaking technique are used to enhance the bandwidth of the amplifier. However, HSPICE is employed to simulate the circuit using 0.18 µm CMOS technology parameters. Finally, the gain of the receiver is 64.3dB, the bandwidth is 3.47 GHz and the power consumption is 980.3µW under a single 1.5V supply.

Keywords:

optical communication , Transimpedance , Amplifier , Limiting Amplifier , Inductive Peaking , Low Power