Analysis and simulation of novel CNTFET based full adders

Ternary logic circuits have advantage over the corresponding binary counterparts with respect to area andinterconnect complexity. CNFET technology is ideal to implement ternary logic circuits because the threshold voltageof CNFETs depends on the physical dimensions of their channel. The Full Adder is one of the most important and basicunits of mathematic circuits that is the basic structure of many complex systems. Moreover, serial and serial-parallelmathematic processes can be carried out faster and more operative error-detection and error-correction codes can beemployed in ternary logic implementations. In this paper several state of the art CNTFET based full adder have beeninspired. The presented structure reduces the delay of the Ternary Full Adder and has high driving capability. Theproposed Ternary Full Adder is simulated at varying supply voltages and temperatures using different frequencies bythe Synopsys HSPICE circuit simulator.

Keywords:

CNTFET , Full Adder , Ternary logic