Hardware Implementation of LIF and HH Spiking Neuronal Models

This paper presents a hardware implementation of both Hodgkin-Huxley (HH) and Leaky Integrate and Fire (LIF) spiking neuronal models. FPGA is used as digital platform due to flexibility and reconfigureability. The proposed neural models are simulated by MatLab and the results are compared with the HDL software’s output in order to evaluate the design. Simple architecture uses two counters and a comparator used as the main part of leaky Integrate and Fire model. For the Hodgkin and Huxley model a Look Up Table based structure is utilized. Although it consumes large amount of area, it results more reasonable propagation delay time hence higher operating frequency. The proposed architectures are evaluated on Stratix III device using Quartus II simulator. Maximum operating frequency of 583 MHz (limited to 500 MHz due to the device port rate) and 76 MHz are achieved for the LIF and HH architectures respectively.

Keywords:

Spiking neural network , LIF Model , HH Model , FPGA implementation