Akram Reza - Department of Computer Engineering, Shahr-e-Qods Branch, Islamic Azad University, Tehran, Iran
Parisa Jolani - Department of Computer Engineering, Science and Research Branch, Islamic Azad University, Tehran, Iran.
Midia Reshadi - Computer Engineering Department, Science and Research Branch, Islamic Azad University,Tehran,Iran

By increasing, the complexity of chips and the need to integrating more components into a chip has made network –on- chip known as an important infrastructure for network communications on the system, and is a good alternative to traditional ways and using the bus. By increasing the density of chips, the possibility of failure in the chip network increases and providing correction and fault tolerance methods is one of the principles of today s chip design. Faults may have undesirable effects on the correct system operation and system performance. In this paper the communication infrastructure failure has been considered as same as link and router failure and the fault tolerance low cost routing algorithm has been suggested base on local fault information By using quad neighbor fault information to avoid back tracking in routing in order to select possible minimal path to destination. In this article, we have suggested cost aware fault tolerance (CAFT) routing algorithm. Our contribution in this algorithm is minimum local fault information, minimum routing decision overhead by implementing routing logic base and determining shortest possible path. For deadlock freedom using an additional virtual channel along Y dimension and prohibiting certain routing turns. In order to evaluate the performance of our routing, we compared it with other fault tolerant routing in terms of average packet latency, throughput and power.

Network-on-Chip, Fault tolerance, Deadlock-free, routing algorithm, 2D-NOC, Adaptive routing