Sepideh Valiollahi - Ph.D. Graduate Electrical and Computer Engineering Department Babol Noshirvani University of Technology Babol, Iran,
Gholamreza Ardeshir - Associate Professor Electrical and Computer Engineering Department Babol Noshirvani University of Technology Babol, Iran,

This paper proposes an ADC with these salient features: 1) implemented completely by digital circuits, 2) using a non-uniform sampling scheme which best suits the parse signals like electroencephalography (EEG) signals, and 3) applying timebased quantization. Digital circuits benefit well from technology scaling, as opposed to serious challenges of analog circuits by scaling. Therefore, although it is a difficult task in mixed-signal circuit design, the proposed ADC is implemented thoroughly bydigital circuits. In addition, the resolution of voltage-based quantizers degrades as a result of reduced power supply in nanometer technology, while time resolution increases by scaling. Therewith, the proposed ADC incorporates delay-line based time quantization. On the other hand, the nyquist rate sampling of sparse signals leads to a huge amount of non-informative data, entailing further compression. This encouraged us to propose a non-uniform scheme based on voltage-controlled oscillator (VCO), which increases the sampling frequency as sparse signals spike. Interestingly, the whole ADC is implemented merely by differential cascoded voltage switch logic (DCVSL) cells. The proposed ADC offers 6 bits resolution and sampling frequency range of 100kHz to 1MHz, while consuming 0.31mW at 1MHz with SNDR of 23.5dB and SFDR of 40.2dB.

all- digital analog to digital converter (ADC); delay lines; differential cascoded switch voltage logic (DCVSL); voltage-controlled oscillator (VCO); non-uniform sampling; time-based quantization