معرفی
استان
تهران
شهر
تهران
سمتهای علمی و اجرایی حسین اسدی در مجلات و ژورنال‌های معتبر ایران
- مجله مهندسی کامپیوتر و دانش (هیات تحریریه)
- فصلنامه فناوری اطلاعات و ارتباطات انتظامی (هیات تحریریه)
سمتهای علمی و اجرایی حسین اسدی در کنفرانس ها و نشستهای معتبر ایران
- دانشگاه صنعتی شریف (عضو هیات علمی)
- بیست و دومین کنفرانس ملی سالانه انجمن کامپیوترایران (دبیر علمی)
مقالات بین المللی حسین اسدی
"RC-RNN: Reconfigurable Cache Architecture for Storage Systems Using Recurrent Neural Networks", Institute of Electrical and Electronics Engineers (IEEE), (2022), Vol 10, No 3: 1492-1506
"Quick Generation of SSD Performance Models Using Machine Learning", Institute of Electrical and Electronics Engineers (IEEE), (2022), Vol 10, No 4: 1821-1836
"CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers", Institute of Electrical and Electronics Engineers (IEEE), (2022), Vol 33, No 10: 2304-2317
"Evaluating Reliability of SSD-Based I/O Caches in Enterprise Storage Systems", Institute of Electrical and Electronics Engineers (IEEE), (2021), Vol 9, No 4: 1914-1929
"ETICA: Efficient Two-Level I/O Caching Architecture for Virtualized Platforms", Institute of Electrical and Electronics Engineers (IEEE), (2021), Vol 32, No 10: 2415-2433
"A Modeling Framework for Reliability of Erasure Codes in SSD Arrays", Institute of Electrical and Electronics Engineers (IEEE), (2020), Vol 69, No 5: 649-665
"A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches", Institute of Electrical and Electronics Engineers (IEEE), (2020), Vol 69, No 2: 594-610
"An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories", Institute of Electrical and Electronics Engineers (IEEE), (2019), Vol 68, No 8: 1114-1130
"TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches", Institute of Electrical and Electronics Engineers (IEEE), (2019), Vol 68, No 3: 455-470
"Estimating and Mitigating Aging Effects in Routing Network of FPGAs", Institute of Electrical and Electronics Engineers (IEEE), (2019), Vol 27, No 3: 651-664
"Dependability Analysis of Data Storage Systems in Presence of Soft Errors", Institute of Electrical and Electronics Engineers (IEEE), (2019), Vol 68, No 1: 201-215
"An Efficient SRAM-Based Reconfigurable Architecture for Embedded Processors", Institute of Electrical and Electronics Engineers (IEEE), (2019), Vol 38, No 3: 466-479
"An Efficient Hybrid I/O Caching Architecture Using Heterogeneous SSDs", Institute of Electrical and Electronics Engineers (IEEE), (2019), Vol 30, No 6: 1238-1250
"An Analytical Model for Performance and Lifetime Estimation of Hybrid DRAM-NVM Main Memories", Institute of Electrical and Electronics Engineers (IEEE), (2019), Vol 68, No 8: 1114-1130
"A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry", Institute of Electrical and Electronics Engineers (IEEE), (2018), Vol 65, No 7: 2196-2209
"ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization", Institute of Electrical and Electronics Engineers (IEEE), (2018), Vol 29, No 7: 1605-1620
"ReCA: An Efficient Reconfigurable Cache Architecture for Storage Systems with Online Workload Characterization", Institute of Electrical and Electronics Engineers (IEEE), (2018), Vol 29, No 7: 1605-1620
"A Resistive RAM-Based FPGA Architecture Equipped With Efficient Programming Circuitry", Institute of Electrical and Electronics Engineers (IEEE), (2018), Vol 65, No 7: 2196-2209
"Modeling Impact of Human Errors on the Data Unavailability and Data Loss of Storage Systems", Institute of Electrical and Electronics Engineers (IEEE), (2018), Vol 67, No 3: 1111-1127
"Evaluating impact of human errors on the availability of data storage systems", IEEE, (2017), Vol , No :
"PEAF: A Power-Efficient Architecture for SRAM-Based FPGAs Using Reconfigurable Hard Logic Design in Dark Silicon Era", Institute of Electrical and Electronics Engineers (IEEE), (2017), Vol 66, No 6: 982-995
"Evaluating impact of human errors on the availability of data storage systems", IEEE, (2017), Vol , No :
"A power gating switch box architecture in routing network of SRAM-based FPGAs in dark silicon era", IEEE, (2017), Vol , No :
"Designing Low Power and Durable Digital Blocks Using Shadow Nanoelectromechanical Relays", Institute of Electrical and Electronics Engineers (IEEE), (2016), Vol 24, No 12: 3489-3498
"Stress-aware routing to mitigate aging effects in SRAM-based FPGAs", IEEE, (2016), Vol , No :
"Layout-Based Modeling and Mitigation of Multiple Event Transients", Institute of Electrical and Electronics Engineers (IEEE), (2016), Vol 35, No 3: 367-379
"Introduction: Special Section on Architecture of Future Many Core Systems", Elsevier BV, (2016), Vol 46, No : 219-220
"Guest Editors’ Introduction: Special Section on Emerging Memory Technologies in Very Large Scale Computing and Storage Systems", Institute of Electrical and Electronics Engineers (IEEE), (2016), Vol 65, No 4: 1006-1009
"A Hybrid Non-Volatile Cache Design for Solid-State Drives Using Comprehensive I/O Characterization", Institute of Electrical and Electronics Engineers (IEEE), (2016), Vol 65, No 6: 1678-1691
"A Cache-Assisted Scratchpad Memory for Multiple-Bit-Error Correction", Institute of Electrical and Electronics Engineers (IEEE), (2016), Vol 24, No 11: 3296-3309
"Operating system level data tiering using online workload characterization", Springer Science and Business Media LLC, (2015), Vol 71, No 4: 1534-1562
"On endurance and performance of erasure codes in SSD-based storage systems", Elsevier BV, (2015), Vol 55, No 11: 2453-2467
"FPGA-Based Protection Scheme against Hardware Trojan Horse Insertion Using Dummy Logic", Institute of Electrical and Electronics Engineers (IEEE), (2015), Vol 7, No 2: 46-50
"DiskAccel", ACM, (2015), Vol , No :
"An efficient reconfigurable architecture by characterizing most frequent logic functions", IEEE, (2015), Vol , No :
"A Scalable Dependability Scheme for Routing Fabric of SRAM-Based Reconfigurable Devices", Institute of Electrical and Electronics Engineers (IEEE), (2015), Vol 23, No 9: 1868-1878
"Towards dark silicon era in FPGAs using complementary hard logic design", IEEE, (2014), Vol , No :
"Soft error estimation and mitigation of digital circuits by characterizing input patterns of logic gates", Elsevier BV, (2014), Vol 54, No 6-7: 1412-1420
"Computer Networks and Distributed Systems", Springer International Publishing, (2014), Vol , No :
"Fine-Grained Architecture in Dark Silicon Era for SRAM-Based Reconfigurable Devices", Institute of Electrical and Electronics Engineers (IEEE), (2014), Vol 61, No 10: 798-802
"Emerging Non-Volatile Memory technologies for future low power reconfigurable systems", IEEE, (2014), Vol , No :
"CEDAR: Modeling impact of component error derating and read frequency on system-level vulnerability in high-performance processors", Elsevier BV, (2014), Vol 54, No 5: 1009-1021
"Artificial Intelligence and Signal Processing", Springer International Publishing, (2014), Vol , No :
"A power-efficient reconfigurable architecture using PCM configuration technology", IEEE Conference Publications, (2014), Vol , No :
"On endurance of erasure codes in SSD-based storage systems", IEEE, (2013), Vol , No :
"Low-Cost Scan-Chain-Based Technique to Recover Multiple Errors in TMR Systems", Institute of Electrical and Electronics Engineers (IEEE), (2013), Vol 21, No 8: 1454-1468
"HAFTA: Highly Available Fault-Tolerant Architecture to Protect SRAM-Based Reconfigurable Devices Against Multiple Bit Upsets", Institute of Electrical and Electronics Engineers (IEEE), (2013), Vol 13, No 1: 203-212
"FTSPM: A Fault-Tolerant ScratchPad Memory", IEEE, (2013), Vol , No :
"FARHAD: A Fault-Tolerant Power-Aware Hybrid Adder for add intensive applications", IEEE, (2013), Vol , No :
"CLASS: Combined logic and architectural soft error sensitivity analysis", IEEE, (2013), Vol , No :
"A layout-based approach for multiple event transient analysis", ACM, (2013), Vol , No :