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title

A Seven-Valued Full Adder/Subtractor Architecture

Credit to Download: 1 | Page Numbers 12 | Abstract Views: 89
Year: 2018
COI code: ICELE03_078
Paper Language: English

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Authors A Seven-Valued Full Adder/Subtractor Architecture

  Ali Mokhtari - School of Computer, Iran University of Science and Technology, Tehran Iran
  Peyman Kabiri - School of Computer, Iran University of Science and Technology, Tehran Iran

Abstract:

Current generation of computers is based on binary logic. There are two types of operations executed in this generationi.e., mathematical and logical operations. Logical instructions use binary logic operations while the mathematicaloperations yet again use the mathematical operations based on binary logic. This article introduces a new idea based onMulti-Valued Logic (MVL) to build a full adder. Here mathematical and logical operations are considered separately.The reported work only considers mathematical operation and more specifically the full adder. The proposed full-addercircuit is based on Operational Amplifier (Op-Amp) and uses MVL with seven electrical levels for its design. This workis implemented in voltage mode and it is a step towards a new generation of computers. Schematic, layout, design andtest results for the proposed full-adder are reported in the article.

Keywords:

Multi-valued logic, Multi-valued full adder, Op-Amp based full adder

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https://www.civilica.com/Paper-ICELE03-ICELE03_078.html
COI code: ICELE03_078

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Mokhtari, Ali & Peyman Kabiri, 2018, A Seven-Valued Full Adder/Subtractor Architecture, 3rd International Conference on Electrical Engineering, تهران, انجمن فناوری های نوین, https://www.civilica.com/Paper-ICELE03-ICELE03_078.htmlInside the text, wherever referred to or an achievement of this article is mentioned, after mentioning the article, inside the parental, the following specifications are written.
First Time: (Mokhtari, Ali & Peyman Kabiri, 2018)
Second and more: (Mokhtari & Kabiri, 2018)
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Type: state university
Paper No.: 19175
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