STATIC POWER AWARE APROACH FOR TASK MAPPING ON MULTICORE ARCHITECTURES USING THE IMPERIALIST COMPETITIVE ALGORITHM

Many-core architectures based on Network on chip with regular topologies provide suitable condition for designing a system on chip with many cores. One of the main issues of this type of architecture is the function mapping or a task (or a set of tasks) assignment on chip processors. This is done with different purposes, including reducing energy consumption, declining chip area, and decreasing the execution time. These goals are very influential on overall system performance. In this thesis, a number of proposed methods by heuristic algorithms for task mapping in network on chip, multicore, and full-core architectures are addressed, Then, while the methods are compared, a method based on Imperialist Competitive Algorithm (ICA) is proposed to reduce power consumption. To evaluate the proposed algorithm, simulations have been done using MATLAB and the number of sample graphs are tested for mapping purpose Comparing the simulation results of the proposed algorithm with the results of other similar studies show improvements in runtime and power consumption. Simulation results show that the proposed method is relatively better results will result in less time.

Keywords:

Imperialist Competitive Algorithm (ICA) , Many-core architecture , network on chip , tasks mapping.