Novel Design of Ternary Half Adder Using Single Electron and MOS

Adder is one of the important arithmetic units in computers. In this paper, we investigate the implementation of ternary half adder based on multiple-valued (MV) logic gates using single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. We use hybrid SETMOS universal literal gate which has been proposed by Mahapatra and Ionesco. We apply two 3-radix inputs to the proposed ternary half adder and obtain sum and carry outputs. The logic operation of the proposed ternary half adder is verified by using HSPICE simulator.

Keywords:

ternary half adder , multiple-valued logic , single electron transistor , universal literal gate.Introduction