Design and simulation of a low leakage Flip-flop

Flip-flops are important and widely used components in memory devices that are responsible for storing information. On the other hand, today electronic science has moved towards portable devices with low power consumption; therefore, the issue of power consumption has become more important than ever. Also in the field of Nano electronics, the share of static power consumption has increased. So in this paper, ۳ Master-Slave flip-flops with low leakage power consumption in ۹۰ nm CMOS technology are presented and simulated by Hspice software. The main idea is to use widely used and effective transistor stacking and force stacking and LECTOR technique to reduce leakage power consumption. These three flip-flops are comparable to the reference flip-flops, which were among the new low-consumption flip-flops; Better results in leakage power consumption and power-delay product (PDP) parameter have been shown so that; The proposed flip-flop with the force stacking technique has the lowest power consumption in terms of leakage power and has reduced this power by ۳۷.۷%, then the transistor stacking technique and the LECTOR have reduced the leakage power consumption by ۳۲ and ۱.۶%, respectively. In the PDP parameter clock to output and PDP parameter input to output of the proposed flip-flop with the force stacking technique, there was a ۹.۸% and ۱۷.۱% reduction compared to the reference flip-flop, respectively.

Keywords:

master-slave , flip-flop , leakage power , PDP