Performance Analysis of Zero Crossing DPLL with Linearized Phase Detector

This work introduces a new structure of Zero Crossing Digital Phase Locked Loop with Arc Sine block (ASZCDPLL) to linearize the phase difference detection, and enhance the loop performance. The new loop has faster acquisition, less steady state phase error, and wider locking range as compared to the conventional ZCDPLL. The locking range improvement and faster acquisition have been confirmed through simulation. The loop has been implemented and tested in real time using Texas Instruments TMS۳۲۰C۶۴۱۶ DSP development kit.

Keywords:

non-uniform sampling , digital phase locked loops , zero crossing DPLL