A Generalized Algorithm for Switch Reduction in Multioutput Single-Phase Inverters with/without Z-source impedance network

A new algorithm is proposed in this paper for switch reduction in multi-output single-phase converters. The idea is first explained by introducing the dual-output six-switch inverter and then generalized into the switch reduction of m-output topology. Two modes of operation are defined for the proposed converter and the modulation scheme of each mode is devised. To compensate for the reduced dc bus utilization, a general algorithm is also proposed for employing Z-source impedance (ZSI) network in m-output configuration. Simulation results validated the veracity of the proposed algorithm.

Keywords:

Multi-output inverter , reduced switch count inverter , Nine-switch converter