Low Power XOR/XNOR-based TGPL flip flop in submicron technology

Flip-flops are widely used as one of the main units in the design of digital circuits and are the main factor in the power loss of the clock network. Therefore, having a flip-flop with low power and high speed leads to the creation of an optimal digital system. One of the families of fast flip-flops is explicit pulsed flip flop such as: TGPL. Therefore, in this paper, two explicit pulsed flip flops with low power consumption in submicron technologies are presented. These new pulsed flip-flops have an external pulse generator circuit based on XOR and XNOR gates, which provided better performance than the NAND-based pulse generator circuit. Comparing these flip-flops with TGFF had these results. In ۹۰ nm technology, XOR-based TGPL and XNOR-based TGPL flip-flops have reduced dynamic power consumption by ۱۸.۱۸% and ۱۴%, respectively. Also, in ۴۵ nm technology, XNOR-based TGPL and then XOR-based TGPL flip-flop have reduced the dynamic power consumption by ۲۰.۹۷% and ۱۹%, respectively.Also, due to very low power consumption, the lowest value of the PDPD_Q parameter corresponds to the proposed XNOR-based TGPL flip-flop and this parameter has been reduced by ۴۸.۳۷% and ۴۵.۶۷% in ۹۰ and ۴۵ nm technology, respectively, compared to TGFF flip-flop

Keywords:

pulsed flip-flop , explicit , power consumption , PDP