A Novel Architecture of Masked Logic Cells for Side-Channel Attacks

Side-channel attacks are attacks against cryptographic devices that are based on information obtained by leakage into cryptographic algorithm hardware implementation rather than algorithm implementation. Power attacks are based on analyzing the power consumption of a corresponding input and obtaining access to this method. The power profile of the encryption circuit maintains an interaction with the input to be processed, allowing the attacker to guess the hidden secrets. In this work, we presented a novel architecture of masked logic cells that are resistant to power attacks and have reduced cell numbers. The presented masking cell reduces the relationship between the actual power and the mathematically approximated power model measured by the Pearson correlation coefficient. The security aspect of the logic cell is measured with the correlation coefficient of the person. The proposed mask-XOR and mask-AND cells are ۰.۰۰۵۳ and ۰.۳respectively, much lower than the standard XOR and AND cells of ۰.۱۳۴ and ۰.۳۷۲respectively.

Keywords:

Side-Channel Attack , Power Attack , Mask Cell , Correlation , Data hiding , Hardware-Security