Design and Qualitative Analysis of Hetero Dielectric Tunnel Field Effect Transistor Device

A Hetero Dielectric Tunnel field effect transistor with the spacer on both sides of the gate is proposed in this paper. The performance and characteristics of Hetero Dielectric Tunnel field effect transistor using the ATLAS Technology Computer-Aided Design in ۵nm regime were analyzed. The band-to-band tunneling leakage current will be reduced by introducing heterojunction and hetero dielectric spacer material in the proposed structure. In Hetero Dielectric Tunnel field effect transistor, double metal gate and high-k dielectric spacer improves high on the current and subthreshold swing. The high-k dielectric Hafnium oxide spacer is placed on both sides of the source and drains to import the tunneling mechanism. The proposed device in the ۵nm node has improved DC characteristics such as a High ON-state current of ۱.۶۸ x ۱۰-۵ Amp & OFF-state Current reduced from ۷. ۸۳x ۱۰-۱۱ Amp to ۵.۱۳ x ۱۰-۱۲ Amp and ION / IOFF ratio has increased from ۳.۲۲ x ۱۰۵ to ۳.۲۷ x ۱۰  compared to conventional dual gate Tunnel field effect transistor. Therefore, this device is suitable for low power applications

Keywords:

High K Dielectric Materials , Tunnel Field Effect Transistor , Hafnium Oxide , Drain current , Technology Computer Aided Desisn