Design Issues for Low Voltage Low Power CMOS Folded Cascode LNAs
Publish place: majlesi Journal of Electrical Engineering، Vol: 6، Issue: 3
Publish Year: 1391
نوع سند: مقاله ژورنالی
زبان: English
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شناسه ملی سند علمی:
JR_MJEE-6-3_006
تاریخ نمایه سازی: 3 آبان 1402
Abstract:
Design and simulation results of fully integrated ۵-GHz CMOS LNAs are presented in this paper. Three different input impedance matching techniques are considered. Using a simple L-C network, the parasitic input resistance of a MOSFET is converted to a ۵۰ Ω resistance. As it is analytically proven, that is because the former methods enhance the gain of the LNA by a factor that is inversely proportional to MOSFET’s input resistance. The effect of each input impedance matching on the amplifier’s noise figure and gain is discussed. By employing the folded cascode configuration, these LNAs can operate at a reduced supply voltage and thus lower power consumption. To address the issue of nonlinearity in design of low voltage LNAs, a new linearization technique is employed. As a result, the IIP۳ is improved extensively without sacrificing other parameters. These LNAs consume ۱.۳ mW power under a ۰.۶ V supply voltage.
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Authors
Ehsan Kargaran
Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran
Mohammad Javad Zavarei
Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran
Nahid Fatahi
Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran
Seyedeh Sara Hassani
Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran
Khalil Mafinezhad
Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran
Hooman Nabovati
Microelectronic Laboratory, Sadjad Institute of Higher Education, Mashhad, Iran
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