A Low-Cost Multi-Sized HEVC Core Transform Using Time-Multiplexed DCT Architectures
Publish Year: 1401
نوع سند: مقاله ژورنالی
زبان: English
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JR_JOAPE-10-2_006
تاریخ نمایه سازی: 13 آبان 1402
Abstract:
High Efficiency Video Coding (HEVC) is one of the latest coding standards targeting high-resolution video contents. Due to the high complexity of the existing hardware implementation, this paper presents the low-cost and efficient DCT architectures for HEVC, which are able to perform DCT operation of multiple transform sizes in a single unified architecture. Our objective is to reuse the hardware resources in a DCT architectures using configurable constant multipliers as well as reducing the hardware cost and trading off between hardware complexity and efficiency. We propose three different shift-and-add units with different hardware cost and throughput. The main advantage of the proposed architectures over the existing architectures is a lower hardware and it can also perform DCT transform of different transform units which is available in HEVC standard. The experimental results over ۹۰-nm technology show that the proposed ۲D-DCT architecture #۱ archives the lowest hardware cost amongst the rest of the architectures with around ۵۷% reduction in gate count, on average. The unfolded ۲D-DCT architectures #۲ and #۳ offer the moderate reduction in gate count around ۴۷%, on average, with a moderate throughput. Apart from architectures #۱, #۲, and #۳, we also develop a reusable architecture by adding an extra ( )-point DCT alongside the main DCT.
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Authors
R. Younesi
Department of Electrical Engineering, Faculty of Engineering, Islamic Azad University, Saveh Branch, Saveh, Iran
J. Rastegar
Department of Electrical Engineering, Faculty of Engineering, Islamic Azad University, Saveh Branch, Saveh, Iran
M. Rastgarpour
Department of Computer Engineering, Faculty of Engineering, Islamic Azad University, Saveh Branch, Saveh, Iran
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