Hardware Implementation of Interval Type-2 Fuzzy Logic Controller

In this paper design of a general-purpose Interval Type-2 Fuzzy Logic Controller (IT2 FLC) is presented. For the fuzzifier block, a new fully programmable IT2 membershipfunction generator (MFG) circuit based on Type-1(T1) MFG is proposed that uses a new method for slope tuning. Theproposed slope tuning method, leads to smaller active area and also significantly smaller total die area by reducing the numbers of required pins in comparison with previous methods. Type-reducer block is designed based on the Nie-Tan typereduction method which reduces hardware complexity.Moreover, a modified version of multiplier is employed in the defuzzifier block which reduces the chip area and enhances the speed performance. Also, a new min circuit is presented to realize the inference block which is perfectly compatible with other blocks. Small area, low power consumption andespecially suitable programming method, makes the proposed FLC suitable for general-purpose applications. The proposedFLC has two inputs with one output that can be implemented in 0.028mm2 in 0.18μm CMOS technology. The maximum delay of the proposed FLC is about 157 ns that corresponds to 6.37 MFLIPS (fuzzy logic inference per second).Power consumption of the proposed FLC is 4.64mW.

Keywords:

IT2 Fuzzifier , IT2 Inference Engine , IT2 Output Processor , Type-Reducer , Defuzzifier